A memory cell usually contains a storage device and a device for accessing the storage device. The storage device is either one device or a plurality of devices which are used to store at least one binary bit value (i.e. a logic zero or a logic one). For dynamic random access memories (DRAMs), the storage device is a capacitor. For static random access memories (SRAMs), the storage device is a pair of inverters connected in a ring to form a flip-flop. In an electrically erasable programmable read only memory (EEPROM), an electrically programmable read only memory (EPROM), and a flash EEPROM device, the storage device is a floating gate electrode.
For dynamic random access memories (DRAMs), the device for accessing the storage device is typically an N-channel transistor or several transistors in series (i.e. decoder logic and a select gate). For static random access memories (SRAMs), the device for accessing the storage device is a pair of N-channel transistors or two strings of transistors connected in series. One transistor reads/writes the binary bit value to the SRAM cell and the other transistor reads/writes the complement of the binary bit value to the SRAM cell. In each of an electrically erasable programmable read only memory (EEPROM), an electrically programmable read only memory (EPROM), and a flash device, the device for accessing the storage device is a select gate which is usually one of either a P-channel transistor, an N-channel transistor or a plurality of transistors connected in series.
Anytime a transistor or a like device is placed in series with a bit line, a power supply line, a word line, or any conductive interconnect, or a threshold voltage drop across the transistor channel region affects the voltage/current passed through the conductive interconnect. This voltage/current effect may necessitate that higher voltage supplies be used, or may result in a bit line value being difficult to properly write or read.
For example, in an EEPROM, a certain voltage between a source, a drain, and a floating gate is required in order to program and erase the EEPROM properly. A select gate having a voltage drop in series with the floating gate transistor results in a higher select gate voltage being required in order to obtain the correct voltage differences within the EEPROM. In the case of EEPROMs, a power supply voltage of roughly 18 to 22 volts is required due to a transistor select gate and decoding logic voltage drop which is in series with the bit line. For a flash device or an EPROM device, a lesser power supply is required to operate properly. EPROMs and flash devices typically require a power supply voltage within the range of 10 volts to 14 volts.
Given the voltage values above, the integration of EEPROM technology with flash or EPROM devices requires the use of two power supplies. One supply provides roughly 20 volts for the EEPROMs, and the other supply provides roughly 12 volts for the EPROMs/flash devices. Due to the fact that a 20 volt supply voltage is required to support EEPROM usage, an entire integrated circuit (IC) which includes the EEPROM cells must be made more robust to avoid voltage breakdown. The overall process becomes more constrained than necessary for producing functional logic, flash devices, EPROM devices, and other circuits due to the 20 volt supply interconnect and potentials. Device isolation, transistor latch-up, and junction leakage currents become a bigger problem at higher voltages. The multiple power supplies may require that the doping concentrations of integrated circuit well regions and diffusions be different for each device (i.e.
EEPROM, flash, EPROM, logic, etc.) in order to optimize device performance. In general, lower voltages are desired for integrated circuit reliability and ease of manufacturing.